TELLTALE: Usage-Evident Electronic Components for Self-Attestation throughout the Supply Chain

The TELLTALE Project proposes innovative research and development to protect the electronic component supply chain from recycled components which are purported to be new. The approach is to provide the capability for devices to self-attest their usage status based upon irreversible physical characteristics which manifest during host circuit operation. This usage information is transmitted upon demand over an encrypted transmission channel for cumulative historical record-keeping in the U.S. government-maintained central database. The result of the project will be new technological capabilities for electronic devices to self-attest their usage status, provide a searchable list of known used and/or pristine components, and a sortable list of parts in descending order of wear for usage-graded bidding by contractors, and to transmit this information over a dielet-resonant electrically-small antenna. Thus, the TELLTALE project will protect the supply chain from recycled parts, and also enable the sustainability of the resource pool for long product lifecycles. TELLTALE provides assurance that electronic components are indeed new and also facilitates procurement based upon components’ aging properties in a trusted manner. 1. Current Vulnerabilities to the Electronic Component Supply Chain A substantial innovation of TELLTALE is to bestow components with a robust yet minimally-intrusive capability to provide assurances that they are new or used. This addresses part of the threat referred to as chip counterfeiting which includes 1) inappropriate marketing: chip vendors re-mark lower grade (commercial-level rated) chips as higher grade (military-level rated chips); 2) chip recycling: workers unsolder chips from used PCB boards for resale as new; and 3) chip faking: encountered at times for obsolete parts. This proposal addresses exposure 2) above using physical differences between new and used electronic components. Leveraging these differences to allow chips to self-attest their usage status would mitigate serious counterfeiting challenges cited in the literature [Martin 2010] [GAO 2010] [Gorman 2012] [DoC 2010] [Villasenor 2013]: 1. companies and organizations assume that others in the supply chain are testing parts, 2. many government and military contractors skip testing due to lack of expertise and cost, 3. lack of traceability due to cost and jurisdictional boundaries in the international marketplace, 4. insufficient visibility into chip accountability regarding sale and especially use, and 5. record-keeping of counterfeit incidents is limited because of the reluctance to report them. These exposures facilitate the risk that every legitimate device manufacturer is susceptible to having their parts used and then later re-introduced into the supply chain as new. 1.1 Need for Usage-Evident Electronic Components Given the vulnerabilities identified above, a complementary technique of usage information is needed to provide 100% assurance of preventing the recycling of parts. Clearly, even the robust part identification mechanism provided by the dielet would not preclude recycling in many scenarios, such as the following example. Here, an exposure remains that a newly manufactured part may be scanned to record its ID upon production. Though after scanning it may be subsequently sold to a distributor who instead of warehousing a large quantity of parts, sells one or more instances. The sold parts can then later re-enter the supply chain as recycled parts, yet may still be listed in the secure central database as new. The database would lack any indication of this exposure and have no control over it, especially if a covert internet marketplace helps guide the returned parts back to the original distributor. The part could be at its end of life yet still be procured as new. Even worse, the component may be damaged during previous use, yet still installed as new. One direct approach for identifying exposures from recycled parts is provision of a robust indicator that would be considered to be usage-evident. This property is analogous to the intrusion detection capability of being “tamper evident.” Likewise, the provision of a tamper indicator doesn’t preclude tampering, but it does provide irrevocable evidence of an intrusion. Likewise, the new class of usageevident electronic components proposed herein does not preclude a chip’s prior usage, but expounds every chip’s own constructive evidence that the device has been used. The premise of TELLTALE is that it is essential to maintain a proper partition of elements within the supply chain into mutually-exclusive subsets of new and used components. Thus, we propose effective and robust techniques which allow every dieletequipped device to robustly identify which of these subsets it belongs to. 1.2 Self-Attestation of Component Usage The Concept of Operation (CONOP) of a TELLTALE usage-evident tracked part depicts the scenario where the component to be tested is scanned on a device where a dielet is embedded. After exchange of an encrypted handshake between the dielet and the secure server, status information is transmitted. As indicated in green text, the novelty of the proposed TELLTALE approach is that not only the status of the passive sensors which are used to verify the integrity of the dielet are exchanged, but also usage information regarding the host chip is exchanged. This may include New/Used Status (NUS), as well as a graded Usage Profile (UP). As exemplified, there is a need for the device to “self-attest” its usage to provide robust on-demand usage-appraisal information to the central database. In the TELLTALE design, persistent irrevocable knowledge of usage accumulated by the device is transferred upon scanning. Once the NUS and/or UP is recorded in the database, this information can enhance the sustainability of the supply-chain. UP information available on a part-by-part basis may be useful to maintain a gracefully-degradable supply chain so that it is known which of the available parts on-hand are least degraded. For example, a sort or search of the parts in the marketplace or even already procured, which have a UP which is minimal or at least meets requirements of the immediate request during a mission, can be performed. Thus, TELLTALE brings complementary techniques of “Usage Evidence” which provides incremental “Usage Grading” in addition to robust part identification. Section 3 identifies the technical approaches proposed to achieve such capabilities. 2. TELLTALE Concept of Operation 2.1 Passive vs. Active Aging Indicator Logic Phase 1 will begin with research on passive approaches to identify NUS/UP. A logic circuit will be sought to identify a persistent irreversible change in material properties when exposed to operating temperatures. This property would be electrically-sensed, e.g. open, short, change in resistance, capacitance, or transconductance. Alternatively, organic-based PTC thermistors which can undergo hysteresis so that their resistance characteristics change irreversibly may provide an option. While passive approaches are highly preferred, also some minimally-intrusive circuits which do not impact the function of the host’s silicon such as canary aging circuits, would be used as a yardstick for comparison which offer alternatives. The deliverable for this task will be a tradeoff study of the options and a design for the preferred approach. 2.2 Ultra-low Power Lightweight Embedded Processor As shown in Figure 5, a low power processor within the dielet will consist of: 1) Encryption Unit, 2) small footprint Digital-to-Analog Converter (DAC), 3) Control Unit, and 4) RF Generation unit. Functionally, the encryption unit encodes the aging information into a binary sequence so that the resulting sequence cannot be easily intercepted. Next, the encrypted information will be converted into an analog signal by a DAC unit, which drives the RF generation unit to transmit a unique pulse sequence. All these units will be orchestrated by a lightweight hardwired Control Unit. The major challenge is that these units have to be implemented in an ultra-low power fashion in a small footprint. The deliverable is a RTL design of dielet embedded processor. 2.3 Radio-Frequency (RF) Energy Harvester Energy harvesting [Olgun 2012] converts ambient RF signals to DC supply voltage using on-chip antenna/inductors, RF-DC rectifier, storage capacitor, and voltage regulator. A high efficiency rectifier design is essential for RF energy harvesting. Our previous energy harvesting design replaced a Schottky diode with CMOS technology to be compatible with on-board electronics. The Greinacher principle is used to build a voltage multiplier. The N-stage voltage multiplier consists of a cascade of N low threshold p-channel MOSFETs, which have their gate and source terminals connected. The coupling capacitor in each stage pumps the voltage to a high potential. Each p-channel MOSFET functions as a diode, which switches in cycles. After many duty cycles, p-channel transistors and on-chip capacitors convert the RF signal to a DC potential. To improve the RF-DC rectifier efficiency, threshold voltage cancellation is utilized. The deliverable is a RF Energy Harvester design for the dielet. 2.4 On-Dielet Oscillator The current-starved Voltage Controlled Oscillator (VCO) design for the dielet will be delivered. The VCO will achieve the required oscillator frequency and digital pulse for on-dielet CMOS circuits to operate. The drain current of the current-starved VCO is controlled by the gate voltage of current sources, which determines the frequency. Power will be supplied from the on-chip RF energy harvesting design above. Figure 5: Ultra-Low Power Lightweight Embedded Processor 3. Robust Record-keeping of Device Usage Transcript Our technical approach to measure and record device usage is conceptually analogous to the idea of an hourglass or sandglass. We use pre-stored electronic charges to measure and indicate the usage of our targeted device. Once the targeted IC device initiates its usage, we use circuit means to control the rate of charge leakage, therefore measuring the amount of unleaked electronic charge can indicate the device usage time. To record device usage reliably and securely, we propose a three-part solution. First, at the initial scanning with a probe, a fixed amount of electrons will be deposited to an electron trap shown in Figure 6. This electron trap will only be used once, because as soon as the deposited charge reach a predefined level, the signal path that transfers these electrons will be blown off automatically. Path cut-off is permanent and irrevocable. We propose to use the device technology similar to Charge Trap Flash (CTF), which is a semiconductor memory technology used in creating non-volatile NOR and NAND flash memory. This technology differs from conventional floatinggate MOSFET technology in the sense that it uses a silicon nitride film to store electrons rather than the doped polycrystalline silicon. Second, we propose a usage grading scheme implemented with the technology similar to the antifuse technology widely used in FPGAs. It consists of multiple antifuse branches that will be blown off automatically after different usage time periods. For example, Fuse 1 will be blown at manufacturing test, Fuse 2 will be blown at 1 hour, Fuse 3 will be blown at 1 week, Fuse 4 will be blown at 3 months, and Fuse 5 will be blown at 1 year of usage. Third, we design a simple circuit to encode how many fuses are blown. This information should be robustly retained. If antifuse voltage is limited or infeasible, a non-volatile flash design will be pursued. In that case, clearing of the flash memory by unforeseen means is mitigated by internal encoding of age count using both trapped and untrapped charge states so bulk clearing of flash will not reset the UP odometer, but instead indicate tampering. There are several potential challenges to realize the above scheme. First, we need to use very reliable charge trap for electron storing. Second, we need to establish a well-defined relationship between the amount of trapped electronic charges and the programming voltage for the antifuses. In fact, depending on our antifuse circuit design, we may need higher programming voltage for fewer remaining trapped charges. For the existing antifuse technology, the programming voltage typically is very high. However, in our case, ideally, we want the programming voltage to be provided only by the trapped charges, which could be very small. Next, the decay of trapped charge needs to be correlated with host usage based on passive properties of temperature or EMI using conventional or nano-materials, or active approaches. Finally, how to design the circuit that encodes the fuse state while making the state information resilient to tampering is challenging because we are given a very limited transistor budget. Nonetheless, the proposed approach aims towards these objectives in that the age saturates at various thresholds while incurring a low device complexity, towards goals of occupying a small area at low cost. 4. General Discussion of Other Research in this Area 4.1 CMOS Aging and Mitigation Approaches Dr. Ronald DeMara has been performing leading research in CMOS anti-aging and adaptive architectures called Logic Wear Leveling (LWL). LWL leverages the stress and recovery cycles of Bias Temperature Instability (BTI) induced aging for energy savings and has been prototyped with a corresponding synthesis flow. Case studies show a reduction in energy consumption of 31.9% at 10 years to meet timing specifications compared to voltage guardbanding [Ashraf 2014a][Ashraf 2014b]. Knowledge of CMOS Figure 6: TELLTALE irrevocable charge trap aging effects which impact delay and energy consumption [Khoshavi 2014] can be extended for aging identification to generate a CMOS device Usage Profile using active techniques with non-intrusive canary circuits. Their embedded realization extends the PI’s experience with adaptive architectures [Ashraf 2013][DeMara 2010][DeMara 2011][Oreifej 2007] [DeMara 2005] and embedded reconfigurable fabrics [Ejnioui 2005a] [Ejnioui 2005b] for resilient design [Imran 2011] [Imran 2012] [Tan 2006a][Tan 2006b]. 4.2 Embedded Controller Design for Ultra-Low Power Operation Dr. Mingjie Lin has been performing leading research in low-energy highly-scaled CMOS processors [Alawad 2014]. Energy efficiency and algorithmic robustness typically are conflicting circuit characteristics, yet with CMOS technology scaling towards 10-nm feature size, both become critical design metrics simultaneously for modern logic circuits. A novel approach demonstrated for both these goals hinges on probabilistic domain transformation where inputs are sampled through probabilistic means and could be considered for extension to low-energy data collection of device sensors. 4.3 RF Energy Harvesting TELLTALE Co-PI Dr. Peter Yuan has been performing leading research in energy harvesting by development of a novel wireless electric power transfer system for space applications [Varquez 2011] which can be extended and further miniaturized for the dielet. Recent progress in development of RF/analog chip design [Yuan 2012] will also be extended to in the dielet transceiver.